Cusmai, Marco

M.Sc. 2009

He was born in Pavia, Italy, in 1984. He received the Master’s degree in Electronics Engineering from the University of Pavia, Italy, in 2009. During his Master’s thesis, he studied compensation techniques for spur reduction in fractional All-Digital PLLs.

Since 2009 he has been holding a grant from the University of Pavia within the “Studio di Microelettronica”, Pavia, in the RF group. His main research interests are in the field of digital frequency synthesizers and data converters. He is currentenly working on ADPLL design in the CCI Serial Interfaces Team of STMicroelectronics Grenoble, France.


PUBLICATIONS

  • [DOI] C. Weltin-Wu, E. Temporiti, M. Cusmai, D. Baldi, and F. Svelto, “Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 57, iss. 9, pp. 2259-2268, 2010.
    [Bibtex]
    @article{5582167,
      Author = {Weltin-Wu, C. and Temporiti, E. and Cusmai, M. and Baldi, D. and Svelto, F.},
      Date-Modified = {2013-03-22 17:02:06 +0100},
      Doi = {10.1109/TCSI.2010.2071650},
      Issn = {1549-8328},
      Journal = {Circuits and Systems I: Regular Papers, IEEE Transactions on},
      Number = {9},
      Pages = {2259-2268},
      Title = {Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs},
      Volume = {57},
      Year = {2010},
      Bdsk-Url-1 = {http://dx.doi.org/10.1109/TCSI.2010.2071650}}
  • [DOI] E. Temporiti, C. Weltin-Wu, D. Baldi, M. Cusmai, and F. Svelto, “A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation,” Solid-State Circuits, IEEE Journal of, vol. 45, iss. 12, pp. 2723-2736, 2010.
    [Bibtex]
    @article{5604330,
      Author = {Temporiti, E. and Weltin-Wu, C. and Baldi, D. and Cusmai, M. and Svelto, F.},
      Date-Modified = {2013-03-22 16:58:44 +0100},
      Doi = {10.1109/JSSC.2010.2077370},
      Issn = {0018-9200},
      Journal = {Solid-State Circuits, IEEE Journal of},
      Number = {12},
      Pages = {2723-2736},
      Title = {A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation},
      Volume = {45},
      Year = {2010},
      Bdsk-Url-1 = {http://dx.doi.org/10.1109/JSSC.2010.2077370}}
  • [DOI] F. Vecchi, S. Bozzola, E. Temporiti, D. Guermandi, M. Pozzoni, M. Repossi, M. Cusmai, U. Decanis, A. Mazzanti, and F. Svelto, “A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS,” Solid-State Circuits, IEEE Journal of, vol. 46, iss. 3, pp. 551-561, 2011.
    [Bibtex]
    @article{5710437,
      Author = {Vecchi, F. and Bozzola, S. and Temporiti, E. and Guermandi, D. and Pozzoni, M. and Repossi, M. and Cusmai, M. and Decanis, U. and Mazzanti, A. and Svelto, F.},
      Date-Added = {2013-03-22 14:00:16 +0100},
      Date-Modified = {2013-03-22 16:26:40 +0100},
      Doi = {10.1109/JSSC.2010.2100251},
      Issn = {0018-9200},
      Journal = {Solid-State Circuits, IEEE Journal of},
      Number = {3},
      Pages = {551-561},
      Title = {A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS},
      Volume = {46},
      Year = {2011},
      Bdsk-Url-1 = {http://dx.doi.org/10.1109/JSSC.2010.2100251}}