Li, Dan

Postdoctoral Researcher

He received the B.E and M.E degrees in Computer Science from Northwestern Polytechnical University, Xi’an, China in 2004 and 2007, respectively, and the Ph.D. degree in Microelectronics from University of Pavia, Pavia, Italy, in 2013.

From 2007-2009 he was with Nvidia Semiconductor Shanghai R&D center, China, where he worked on custom SRAM circuitry and power characterization. From 2011 he was with Studio di Microelettronica, STMicroelectronics, Pavia, working on 25Gb/s CMOS optical receiver circuitry for 100GbE optical link and silicon phonics related applications. His doctoral study was mainly focused on low-noise design techniques for high-speed optical receiver front-ends.

His current research interests include optical transceiver design and broadband circuits on highly scaled CMOS and SiGe.


CONTACT

E-mail: dan.li@unipv.it


PUBLICATIONS

  • [DOI] D. Li, G. Minoia, M. Repossi, D. Baldi, E. Temporiti, A. Mazzanti, and F. Svelto, “A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4,” in ESSCIRC (ESSCIRC), 2012 Proceedings of the, 2012, pp. 221-224.
    [Bibtex]
    @inproceedings{6341298,
      Author = {Li, D. and Minoia, G. and Repossi, M. and Baldi, D. and Temporiti, E. and Mazzanti, A. and Svelto, F.},
      Booktitle = {ESSCIRC (ESSCIRC), 2012 Proceedings of the},
      Date-Added = {2013-03-22 10:46:22 +0100},
      Date-Modified = {2013-03-22 17:03:17 +0100},
      Doi = {10.1109/ESSCIRC.2012.6341298},
      Issn = {1930-8833},
      Pages = {221-224},
      Title = {A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4},
      Year = {2012},
      Bdsk-Url-1 = {http://dx.doi.org/10.1109/ESSCIRC.2012.6341298}}