Loi, Fabrizio

Ph.D. candidate

He was born in Vizzolo Predabissi, Milano, Italy, in 1985. He received the M.S. degrees with honors in Electronics Engineering from the University of Pavia, Pavia, Italy, in 2012. During his Master degree thesis he studied High Linearity FIR Equalizer for serial communications applications.

Since november 2012 he is working toward the Ph.D. in Microelectronics at the same University with Professor Andrea Mazzanti as Advisor. His current research interests cover the development of multi-Gbps CMOS transceivers for copper backplane serial communications.


CONTACT

E-mail: fabrizio.loi@unipv.it


PUBLICATIONS

2015

  • [DOI] F. Loi, E. Mammei, F. Radice, M. Bruccoleri, S. Erba, M. Bassi, and A. Mazzanti, “A 25-Gb/s FIR equalizer based on highly linear all-pass delay-line stages in 28-nm LP CMOS,” in Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE, 2015, pp. 303-306.
    [Bibtex]
    @INPROCEEDINGS{7337765, 
    author={F. Loi and E. Mammei and F. Radice and M. Bruccoleri and S. Erba and M. Bassi and A. Mazzanti}, 
    booktitle={Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE}, 
    title={A 25-Gb/s FIR equalizer based on highly linear all-pass delay-line stages in 28-nm LP CMOS}, 
    year={2015}, 
    pages={303-306}, 
    keywords={CMOS integrated circuits;FIR filters;all-pass filters;delay lines;equalisers;radio receivers;radiofrequency integrated circuits;4-tap FIR equalizer;BER;FIR filters;LP CMOS;SNR;adaptation techniques;bit rate 25 Gbit/s;channel frequency response;current 25 mA;high speed wireline receivers;input signal amplitude;linear all-pass delay-line stages;loss 20 dB;loss channel;size 28 nm;voltage 1 V;voltage 900 mV;Adders;Bit error rate;CMOS integrated circuits;CMOS technology;CMOS;FIR;adaptive equalizer;all-pass;wireline}, 
    doi={10.1109/RFIC.2015.7337765}, 
    month={May},}

2014

  • [DOI] E. Mammei, F. Loi, F. Radice, A. Dati, M. Bruccoleri, M. Bassi, and A. Mazzanti, “8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, 2014, pp. 142-143.
    [Bibtex]
    @INPROCEEDINGS{2014Mammei,
      author = {Mammei, E. and Loi, F. and Radice, F. and Dati, A. and Bruccoleri,
      M. and Bassi, M. and Mazzanti, A.},
      title = {8.3 A power-scalable 7-tap FIR equalizer with tunable active delay
      line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS},
      booktitle = {Solid-State Circuits Conference Digest of Technical Papers (ISSCC),
      2014 IEEE International},
      year = {2014},
      pages = {142-143},
      month = {Feb},
      doi = {10.1109/ISSCC.2014.6757373},
      issn = {0193-6530},
      keywords = {CMOS integrated circuits;FIR filters;equalisers;integrated optoelectronics;local
      area networks;low-power electronics;optical delay lines;optical fibre
      dispersion;optical pulse shaping;space division multiplexing;10GBASE-LRM
      standard;FIR filter;LAN;MMF;active delay line;bit rate 10 Gbit/s
      to 25 Gbit/s;channel response;electronic dispersion compensation;local
      area networks;low power CMOS;modal dispersion;multimode fiber EDC;nonlinear
      equalizer;power scalable 7-tap FIR equalizer;pulse shaping;signal
      processing;size 28 nm;space division multiplexing;CMOS integrated
      circuits;Delay lines;Equalizers;Finite impulse response filters;Optical
      fiber LAN;Optical fiber dispersion;Solid state circuits},
      timestamp = {2015.03.04}
    }
  • [DOI] E. Mammei, F. Loi, F. Radice, A. Dati, M. Bruccoleri, M. Bassi, and A. Mazzanti, “Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS,” Solid-State Circuits, IEEE Journal of, vol. 49, iss. 12, pp. 3130-3140, 2014.
    [Bibtex]
    @ARTICLE{2014Mammeia,
      author = {Mammei, E. and Loi, F. and Radice, F. and Dati, A. and Bruccoleri,
      M. and Bassi, M. and Mazzanti, A.},
      title = {Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer
      for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS},
      journal = {Solid-State Circuits, IEEE Journal of},
      year = {2014},
      volume = {49},
      pages = {3130-3140},
      number = {12},
      month = {Dec},
      doi = {10.1109/JSSC.2014.2345770},
      issn = {0018-9200},
      keywords = {CMOS integrated circuits;FIR filters;compensation;continuous time
      filters;equalisers;integrated optoelectronics;operational amplifiers;optical
      delay lines;optical fibre amplifiers;optical fibre dispersion;optical
      fibre filters;LP CMOS technology;active delay line elements;bit rate
      10 Gbit/s to 25 Gbit/s;bit rate 400 Gbit/s;circuit topology;dispersion
      compensation;filter tap coefficients;input data-rate variation;input
      data-rates;multimode fiber EDC;multimode fiber links;power 55 mW
      to 90 mW;power efficiency;power-scalable continuous-time 7-tap FIR
      equalizer;programmable transconductors;size 28 nm;test chips;transimpedance
      amplifier;ultra-compact equalizer;CMOS integrated circuits;Delay
      lines;Delays;Equalizers;Finite impulse response filters;Gain;Noise;28
      nm CMOS;FIR equalizer;all-pass;delay line;electronic dispersion compensation;multi-mode
      fiber},
      timestamp = {2015.03.04}
    }