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The ever-increasing data center IP traffic, up to 8.6 zettabytes per year by 2018 with nearly 3× growth since 2013 , requires power-efficient high-speed interconnects. Next generation optical interfaces will adopt 50Gbaud signaling , and minimizing power consumption is key to enable the use of small form-factor optical modules for electro-optical conversion. In this perspective, silicon photonics is an attractive alternative to discrete photonics, lending itself to higher miniaturization at reduced cost . Furthermore, silicon photonics enables co-design of electronics with photonics, thus optimizing transceiver power efficiency. In particular, the electro-optical transmitter constitutes the main source of power consumption. Travelling wave Mach-Zehnder modulator (MZM) architectures are used in discrete photonics realizations as data rate increases, and lend themselves to silicon photonics. However silicon photonics suffers from electrical propagation losses and bandwidth limitations of integrated transmission lines, requiring equalization in the electronic driver to address 50Gbaud operation at moderate consumption and also in advanced node technologies. In this work, we employ a bifilar transmission line determining an electrical propagation loss of ~3dB/mm at 28GHz. Using an equalizer counteracts its effect, applying passive boost and shunt peaking in the pre-driving stage, combined with passive peaking in the load coupling. A 75% increase in the vertical aperture of the optical eye diagram is thus achieved with no power consumption penalty due to the equalizer. The complete electro-optical transmitter, operating at 56Gb/s at 1310nm wavelength, dissipates 300mW and ensures an extinction ratio (ER) higher than 2.5dB. This 56Gb/s silicon photonics transmitter displayes more than 30% power savings with respect to the state-of-the-art .
 E. Temporiti, G. Minoia, M. Repossi, D. Baldi, A. Ghilioni and F. Svelto, “23.4 A 56Gb/s 300mW silicon-photonics transmitter in 3D-integrated PIC25G and 55nm BiCMOS technologies,” 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2016, pp. 404-405.