The release of an unlicensed bandwidth of 7 GHz around 60GHz has opened up a variety of applications including gigabit/s point-to-point links, wireless local area networks (WLANs), short-range high data-rate wireless personal area networks (WPANs), and vehicular radar. In order to hit the market, the cost, size, and power consumption of any solution has to be significantly below what is currently being achieved using compound semiconductor technology. Historically, monolithic microwave integrated circuits (MMICs) have been designed using III-V semiconductor technologies, such as GaAs and InP, which have superior performance compared to CMOS due to their higher electron mobility, higher breakdown voltage, and the availability of high quality-factor passives. Still, a CMOS implementation promises higher levels of integration and reduced cost. In the recent past, we have been active searching solutions for the analog front-end (snapshot activity). This activity is presently carried out in the framework of the European Project ENIAC – Mirandela, aimed at demonstrating a fully transceiver in 32nm CMOS.
One key aspect of the transceiver is the ability to handle wide analog bandwidths, challenging for both the linear processing chain and the frequency reference generator. According to the international regulation IEEE 802.15 WPAN, dedicated channels are 2.16 GHz wide and occupy the frequency range between 57.2 GHz and 65.8 GHz, as shown in Figure 1. The corresponding RF fractional bandwidth is ~14%, mandating an analog front-end fractional bandwidth in excess of 20% considering spreads due to process variations.
Figure 1: Spectrum allocation for Gbit/s wireless communications
A typical front-end gain stage tunes the output capacitive load by means of a second order LC network, thus setting the gain-bandwidth product. At mm-wave frequencies, gain is rare discouraging trading gain for bandwidth. In this work, which extends, we exploit a higher order filter at the inter-stage between front-end blocks with significant improvement of the gain-bandwidth product at the expense of a moderate in-band ripple. This technique has been applied to both LNA and mixer, resulting in an extremely sensitive 65nm CMOS receiver with NF <6.5 dB over >13 GHz bandwidth, verified with experiments on realized prototypes. An in-depth analysis of the proposed inter-stage filter is carried out and a comparison with a standard LC is established.
The receiver, shown in Figure 2, adopts a sliding IF architecture preferred to a direct conversion because it does not require a quadrature high frequency oscillator and to a fixed IF due to a more relaxed synthesizer frequency range requirement.
Figure 2: Block diagram of the integrated receiver
The synthesized local oscillator (LO) frequency and the intermediate frequency (IF) are set to 2/3 and 1/3 the received frequency, respectively. The synthesizer uses an integer-N type II PLL architecture, based on a three-state phase-frequency detector (PFD) – charge pump (CP) combination. By judicious choice of the charge pump current and filter components the integrated phase noise from 10 kHz to 10 MHz offset is -22.5 dBc, enough to assure adequate signal to noise ratios even at highest communications rates. The synthesizer frequency range is 16% around 40.6 GHz.
Figure 3: Chip microphotograph