Advances in communications interface design are required to extend performance in applications ranging from networking to storage to traditional computing. Tighter integration of optical and electrical components, improved electrical link power efficiency and increased serial data rates play crucial roles.
A key challenge for future backplane interconnect is delivering high rate over channels with increasing loss under stringent power performance. With efficient electrical-optical conversion, integrated silicon photonics offers a path to dramatic channel improvement via the replacement of electrical with optical interconnect. As I/O requirements start being measured in Tb/s for electrical backplane and chip to chip communication, improving area and power efficiency is a necessity. In perspective, enabling 100 Gb/s links are required for future wireline systems.
In this framework, a 45 nm CMOS receiver for backplane communications, based on an un-clocked DFE, has been realized. A bi-dimensional equalization simultaneously adapts the DFE tap value and feedback delay, optimizing both the vertical and horizontal eye opening at the sampler input. Prototypes show error free operation at 12 Gb/s with 39 dB backplane loss. The receiver core measures 0.1 mm2 and consumes 130 mW.