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Design of a CMOS readout chip for the BaBar silicon vertex tracker
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P.F. Manfredi, L. Ratti, V. Re, V. Speziali
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A Silicon Vertex Tracker (SVT) based on five silicon microstrip layers
is used in the BaBar experiment at the Stanford Linear Accelerator
Laboratory. The readout chip for this detector has been developed in
the frame of a collaboration between the University of Pavia, the
Lawrence Berkeley National Laboratory and the University of California
at Santa Cruz. The chip includes 128 analog processing channels, and a
digital section for the data storage and sparse readout. The analog
section, besides low-noise preamplification and shaping, implements an
analog-to-digital conversion based on the Time-over-Threshold (ToT)
technique. The chip was designed and fabricated in the Honeywell
rad-hard CMOS 0.8 um technology. Two versions of the chip are
available, named respectively AToM I and AToM II (A
Time-over-threshold Machine).
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AToM I is used for the readout of the
inner layers of the detector, while AToM II, which has better noise
performances, was optimized for the operating conditions of the outer
layers (detector capacitance of about 35 pF, signal peaking time of
about 400 ns). Both chips were proved to stand up to 2.4 Mrad
integrated dose of 60Co gamma rays (equivalent to a ten year
worst-case operation in the BaBar beam line), without showing any
sizable performance degradation. The complete readout system was
installed in the beam line at the Stanford Linear Accelerator Center
(USA) at the beginning of 1999 and the BaBar experiment began taking
data in May 1999. New radiation damage studies have been performed
recently, confirming that the chip can be operated at the high
luminosity levels of the PEP-II collider.
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