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Design of the analog channel for the silicon strip detector of the BTeV experiment
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P.F. Manfredi, M. Manghisoni, L. Ratti, V. Re,
V. Speziali, G. Traversi
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The front-end processing of the signals from the silicon strip
detector in the BTeV experiment at the Fermi National Accelerator
Laboratory (Fermilab) will be performed by custom-designed ICs. The
readout chip has been developed in the frame of a collaboration
between the University of Pavia, the Istituto Nazionale di Fisica
Nucleare and the Electrical Engineering Department of the Particle
Physics Division at Fermilab. The Fermilab Silicon Strip Readout
(FSSR) chip is a mixed-signal circuit occupying an area of
7.27 x 4.46 mm2. It can be described as including four logic
sections: the core, the programmable registers and digital-to-analog
converters, the programming interface and the data output
interface. The analog section of the FSSR core consists of 128
channels, each connected to a detector strip. The signals from the
strips, after amplification and shaping, are compared to a preset
threshold, generating a logic 1 at the output if a signal exceeding the threshold is
detected. A symmetric baseline restorer is included to achieve baseline shift suppression
but it can be bypassed by a programmable switch. An additional 3 bit
information is provided by a flash-ADC. The charge sensitivity of
the channel can be programmed either to 100 mV/fC or 150 mV/fC by
acting on the preamplifier feedback capacitance and the peaking
time of the signal at the shaper output can be selected
among three values (60 ns, 85 ns, 125 ns). In this way the noise
performances of the chip can be optimized according to the signal
occupancy, preserving the required efficiency.
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The chip was designed and fabricated in the TSMC CMOS
0.25 um technology. Such a process, which features the intrinsic
radiation hardness properties typical of deep submicron technologies,
can be made even more radiation resistant by means of proper layout
solutions, such as enclosed NMOS transistors and guard rings. The
analog section of the chip was simulated and optimized from the
standpoint of noise, comparator threshold dispersion and sensitivity
to variations of process parameters.
The first FSSR prototype was submitted in July 2003 and a second version of the
chip, namely FSSR2, has been submitted at the end of
2004. During 2005 this second version has been thoroughly characterized
through charge scan tests for equivalent noise charge (ENC) and
threshold dispersion measurement. Results were found to be in
agreement with the design specifications. In order to investigate
whether the circuit is suitable to be operated in harsh radiation environment,
some sample of the FSSR2 were exposed to gamma-rays from a cobalt 60 source.
Irradiation did not seem to affect to any extent the properties of the circuit
confirming the extremely high radiation tolerance featured by the FSSR2 chip.
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